Hardware-assisted design verification system using a packet-based protocol logic synthesized for efficient data loading and unloading
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United States of America Patent
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May 30, 2006
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app pub date -
Jun 11, 2001
filing date -
Oct 20, 2000
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Abstract
A system is provided to increase the accessibility of registers and memories in a user's design undergoing functional verification in a hardware-assisted design verification system. A packet-based protocol is used to perform data transfer operations between a host workstation and a hardware accelerator for loading data to and unloading data from the registers and memories in a target design under verification (DUV) during logic simulation. The method and apparatus synthesizes interface logic into the DUV to provide for greater access to the registers and memories in the target DUV which is simulated with the assistance of the hardware accelerator.
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