Techniques for phase shift reduction in a single crystal multiple output clock system
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United States of America Patent
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Oct 25, 2022
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N/A
app pub date -
Jan 21, 2021
filing date -
Jan 21, 2021
priority date (Note) -
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Abstract
Certain aspects of the present disclosure provide a circuit for clock signal generation. The circuit generally includes a plurality of clock generation circuits configured to generate a plurality of clock signals from a clock signal, and a power supply circuit having an output coupled to power supply inputs of the plurality of clock generation circuits. The circuit may also include a capacitor array coupled to the output of the power supply circuit and include a plurality of capacitive elements, the capacitor array being configured to selectively couple each of the plurality of capacitive elements to the output of the power supply circuit based on a quantity of one or more active clock generation circuits of the plurality of clock generation circuits.
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