Method for forming a gate in a semiconductor device

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United States of America Patent

PATENT NO 6451639
APP PUB NO 20020058372A1
SERIAL NO

10036279

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Abstract

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A method of forming a semiconductor device gate including the steps of forming a dummy gate insulating layer on a semiconductor substrate having an isolating field oxide layer, successively depositing a dummy gate silicon layer and a hard mask layer on the dummy gate insulating layer, forming a hard mask layer and patterning the dummy gate silicon layer using the mask pattern as an etch barrier, forming a thermal oxide layer at both sidewalls of the dummy gate silicon layer by thermal oxidation on the resultant structure, forming spacers at both sidewalls of the dummy gate silicon layer, depositing an insulating interlayer on the resultant structure, polishing the insulating interlayer to expose the dummy gate silicon layer, forming a damascene structure by removing the dummy gate silicon and insulating layers, depositing a gate insulating layer and a gate metal layer on an entire surface of the semiconductor substrate having the damascene structure, and polishing the gate metal and insulating layers, thereby preventing the undercut at the bottom corners of a damascene groove.

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Patent Owner(s)

Patent OwnerAddress
HYNIX SEMICONDUCTOR INCSAN 136-1 AMI-RI BUBAL-EUP ICHEON-SI GYEONGGI-DO 467-701

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Jang, Se Aug Kyoungki-do, KR 48 533
Kim, Jae Young Kyoungki-do, KR 155 1001
Kim, Tae Kyun Kyoungki-do, KR 111 1101
Yeo, In Seok Seoul, KR 30 490

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