Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits
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United States of America Patent
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Mar 10, 2009
Grant Date -
Aug 19, 2004
app pub date -
Feb 9, 2004
filing date -
Mar 2, 2001
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Abstract
Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.
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