Method of manufacturing semiconductor device and the semiconductor device manufactured by the method
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United States of America Patent
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May 22, 2007
Grant Date -
May 18, 2006
app pub date -
Nov 4, 2005
filing date -
Nov 12, 2004
priority date (Note) -
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Abstract
The method of manufacturing the semiconductor device that includes a high voltage MOS transistor with high operating voltage under both high and low gate voltages with low-cost is disclosed. When manufacturing the high voltage MOS transistor, a portion of a gate insulation film is removed to form an opening that exposes an outside area of the active area, which is outside of the central area where a gate electrode will be formed. A shallow grade layer is formed by implanting impurities into an opening with an energy that does not permit penetration of impurity ions through the gate insulation film.
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