Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure

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United States of America Patent

PATENT NO 11557532
APP PUB NO 20200402899A1
SERIAL NO

17007821

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Abstract

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A 3D-IC includes a first tier device and a second tier device. The first tier device and the second tier device are vertically stacked together. The first tier device includes a first substrate and a first interconnect structure formed over the first substrate. The second tier device includes a second substrate, a doped region formed in the second substrate, a dummy gate formed over the substrate, and a second interconnect structure formed over the second substrate. The 3D-IC also includes an inter-tier via extends vertically through the second substrate. The inter-tier via has a first end and a second end opposite the first end. The first end of the inter-tier via is coupled to the first interconnect structure. The second end of the inter-tier via is coupled to one of: the doped region, the dummy gate, or the second interconnect structure.

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Patent Owner(s)

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Colinge, Jean-Pierre Hsinchu, TW 161 4549
Diaz, Carlos H Mountain View, US 263 3784
Guo, Ta-Pen Taipei, TW 106 1315
Lin, Yi-Hsiung Hsin-Chu, TW 74 281

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