Solid-state imaging device, signal processing method, and electronic device
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United States of America Patent
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Jun 23, 2020
Grant Date -
Apr 18, 2019
app pub date -
Mar 16, 2017
filing date -
Mar 30, 2016
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Abstract
The present disclosure relates to a solid-state imaging device, a signal processing method, and an electronic device, capable of suppressing an input voltage of comparison apparatus at the time of P-phase input. In the present technology, a signal voltage is clipped at a predetermined voltage (for example, comparative voltage), and the clip is released at the time of D-phase count. With this configuration, the comparative voltage and the signal voltage VSL (initial voltage) do not cross (the comparator is not inverted in the D-phase). Thus, the up/down counter 32 detects this and sets the count of the P-phase to be 0 without counting the P-phase. The present disclosure can be applied to, for example, a CMOS solid-state imaging device.
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