Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics
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United States of America Patent
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Aug 17, 2010
Grant Date -
Feb 12, 2009
app pub date -
Aug 8, 2007
filing date -
Aug 8, 2007
priority date (Note) -
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Abstract
Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.
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