Queue circuit and method for memory arbitration employing same
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United States of America Patent
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Jul 29, 2008
Grant Date -
N/A
app pub date -
Jul 20, 2001
filing date -
Jul 20, 2000
priority date (Note) -
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Abstract
A memory access arbitration scheme is provided where transactions to a shared memory are stored in an arbitration queue. A collapsible queuing structure and method are provided, such that once a transaction is serviced, higher order entries ripple down in the queue to make room for new entries while maintaining an oldest to newest relationship among the queue entries. A queuing circuit having a plurality of registers interconnected by 2:1 multiplexers is also provided. The circuit is arranged such that each register receives either its own current contents or the contents of a higher order register during each register write cycle.
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