Hybrid high-k first and high-k last replacement gate process

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United States of America Patent

PATENT NO 9960162
SERIAL NO

15184405

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Abstract

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An integrated circuit and method with a metal gate NMOS transistor with a high-k first gate dielectric on a high quality thermally grown interface dielectric and with a metal gate PMOS transistor with a high-k last gate dielectric on a chemically grown interface dielectric.

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Patent Owner(s)

  • AGILENT TECHNOLOGIES TEXAS INSTRUMENTS INCORPORATED

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Mehrotra, Manoj Bangalore, IN 73 724
Nandakumar, Mahalingam Richardson, US 103 781
Niimi, Hiroaki Dallas, US 147 1255

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