Hierarchical to physical memory mapped input/output translation
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United States of America Patent
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Jan 29, 2013
Grant Date -
Oct 13, 2011
app pub date -
Apr 12, 2010
filing date -
Apr 12, 2010
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In an embodiment, a translation of a hierarchical MMIO address range to a physical MMIO address range and an identifier of a bridge in a south chip are written to a north chip. A transaction is received that comprises a hierarchical MMIO address. The hierarchical MMIO address that is within the hierarchical MMIO address range is replaced in the transaction with the identifier of the bridge and with a physical MMIO address that is within the physical MMIO address range in the south chip. The transaction is sent to the device that is connected to the bridge in the south chip. The physical MMIO address range specifies a range of physical MMIO addresses in memory in the device.
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