Register scorboarding on a microprocessor chip
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United States of America Patent
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-
Jan 2, 1990
Grant Date -
N/A
app pub date -
Nov 26, 1986
filing date -
Nov 26, 1986
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
When a load instruction is encountered, a read operation is sent to the bus control logic, the register is marked as busy, and execution proceeds to the next instruction. When an instruction is executed, it proceeds providing that its source and destination registers are not marked busy; otherwise the instruction is retried. When data are returned as the result of a read operation, the destination register(s) are marked as not busy.
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