Semiconductor packages with enhanced joint reliability and methods of fabricating the same
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United States of America Patent
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Oct 6, 2009
Grant Date -
Nov 27, 2008
app pub date -
May 19, 2008
filing date -
May 22, 2007
priority date (Note) -
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Abstract
Provided is a semiconductor package with enhanced joint reliability and methods of fabricating the same. The method includes: forming package units including a semiconductor chip interposed between a bottom layer and a top layer; and sequentially stacking the package units on a substrate. The bottom layer and the top layer are formed of a material having a lower modulus than the semiconductor chip. The semiconductor package includes: at least one package unit disposed on a substrate, the package unit including a semiconductor chip having a pad, a bottom layer and a top layer substantially surrounding the semiconductor chip, and a redistribution structure overlying the top layer. The redistribution structure is electrically connected to the pad.
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