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Abstract

An apparatus for comparing and validating digital words uses a single dual-logic transistor arrangement to execute comparison and validation functions. A validation dual-logic circuit is achieved with a first configuration of input connections to the dual-logic transistor arrangement. The validation dual-logic circuit identifies a valid state between a valid bit of a first digital word and a valid bit of a second digital word. A comparison dual-logic circuit is achieved with a second configuration of input connections to the dual-logic transistor arrangement. The comparison dual-logic circuit identifies a match between a selected bit of the first digital word and a corresponding bit of the second digital word. The number of comparison dual-logic circuits used corresponds to the bit length of the digital words being compared. A single output node generates a match signal when the first and second digital words are identical and the validation function is satisfied.

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First Claim