Write-assist and power-down circuit for low power SRAM applications
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United States of America Patent
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Nov 16, 2010
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Aug 25, 2009
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Dec 4, 2006
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Abstract
Described herein are methods and apparatuses for write-assist voltage generation and power-down voltage scaling for static random access memory (SRAM) cells. According to various embodiments, an SRAM cell may include a local power supply voltage node for receiving a power supply voltage generated by a power supply voltage generator circuit, the generated power supply voltage being substantially equal to or less than a global power supply voltage provided to one or more transistors of the SRAM cell during a write-enable or power-down mode.
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