LDMOS device and method for manufacturing same

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 11264497
APP PUB NO 20200235237A1
SERIAL NO

16657096

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Abstract

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Disclosed is an LDMOS device comprising a drift region formed by a selected area of a doped layer of a first conductivity type on a semiconductor substrate, a gate structure comprising a gate dielectric layer and a gate conductive layer which are sequentially formed on a surface of the doped layer of the first conductivity type, a doped self-aligned channel region of a second conductivity type, and a doped layer formed by tilted ion implantation with a first side face of the gate structure as a self-alignment condition. A method for manufacturing an LDMOS device is further disclosed. The channel length is not affected by lithography and thus can be minimized to fulfill an ultralow specific-on-resistance, and the distribution uniformity of the channel length can be improved, so that the performance uniformity of the device is improved.

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Patent Owner(s)

  • SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Qian, Wensheng Shanghai, CN 46 144

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