Single-event effect tolerant latch circuit and flip-flop circuit
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United States of America Patent
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Aug 18, 2009
Grant Date -
Jun 14, 2007
app pub date -
Dec 12, 2006
filing date -
Dec 12, 2005
priority date (Note) -
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status (Latency Note)
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Abstract
Disclosed are a latch circuit and a flip-flop circuit, which are capable of suppressing occurrence of a single-event effect, and, in the event of a single-event transient (SET), elimination adverse effects thereof on the circuit. The latch circuit comprises a dual-port inverter, and a dual-port clocked inverter including no transmission gate to reduce a region of strong electric field to be formed. A delay time is set up in a clock to eliminate adverse effects of the SET, and a leading-edge delayed clock to be entered into one of two storage nodes is generated in such a manner as to delay a transition of the storage node and the entire storage nodes from a latch mode to a through mode while preventing an increase in hold time due to the delay time.
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