Generation of delay values for a simulation model of circuit elements in a clock network
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United States of America Patent
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May 2, 2017
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app pub date -
Apr 22, 2015
filing date -
Apr 22, 2015
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Abstract
An approach for generating delay values for circuit elements in a clock network of a programmable IC includes determining for each clock resource in the clock network, different possible contexts of the clock resource. Each context specifies a combination of possible types of circuit elements in the context. Circuit elements of the possible types are selected from the different contexts, and configuration data is generated for implementation of respective ring oscillator circuits that include the selected circuit elements. The programmable IC is configured with the configuration data, and the programmable IC as configured with the respective ring oscillator circuits is operated. Respective delay values of the selected circuit elements are determined from output of the ring oscillator circuits. The delay values are stored in association with identifiers of the selected circuit elements in a memory arrangement.
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