Clock multipliers using filter bias of a phase-locked loop and methods of multiplying a clock
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United States of America Patent
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Jun 17, 2008
Grant Date -
Feb 22, 2007
app pub date -
Aug 14, 2006
filing date -
Aug 16, 2005
priority date (Note) -
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Abstract
A clock multiplier includes a phase-locked loop (PLL), a bias generator, a counter, a selection circuit, a flip-flop, a phase comparator, a delay controller and a variable delay circuit. The variable delay circuit, which is biased by a delay cell bias signal, delays a reference signal by a first delay time and by a second time that is longer than the first delay time, and generates a first feedback signal corresponding to the first delay time, and a second feedback signal corresponding to the second delay time. Therefore, a clock multiplier may reduce the size of a delay cell and may be designed to be insensitive to changes in environmental conditions, such as a process, a voltage, a temperature, and so on.
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