Impedance adjusting circuit and semiconductor memory device having the same
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United States of America Patent
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Jan 5, 2010
Grant Date -
Jan 1, 2009
app pub date -
Dec 28, 2007
filing date -
Jun 26, 2007
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An impedance adjusting circuit includes: a first calibration resistor circuit configured to be calibrated with an external resistor and generate a first calibration code; a second calibration resistor circuit configured to be calibrated with the first calibration resistor circuit and generate a second calibration code, the second calibration resistor circuit being connected to a first node; and a transmission line circuit configured to be responsive to a control signal to connect the first node to a pin of a system employing the impedance adjusting circuit.
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