Extended length metal line for improved ESD performance
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United States of America Patent
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May 3, 2005
Grant Date -
Sep 30, 2004
app pub date -
Mar 26, 2003
filing date -
Mar 26, 2003
priority date (Note) -
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Abstract
A multi-level metal interconnect structure and method for forming the same for improving a resistance of CMOS transistors to electrostatic discharge (ESD) transient events is disclosed. A semiconductor device including at least one NMOS transistor electrically connected along at least one circuit pathway to an input/output signal source and a reference voltage potential; and, electrically connecting at least the input/output signal source to the at least one NMOS transistor with a metal interconnect line extended in length by compacting at least a portion of the metal interconnect line length portion into a serpentine shape within a predetermined volume of the semiconductor device.
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