Circuit for outputting a data signal following an output enable command signal
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United States of America Patent
Stats
-
Dec 22, 1992
Grant Date -
N/A
app pub date -
Jul 17, 1991
filing date -
Jul 17, 1991
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
The invention provides an output enable control circuit with a three gate delay. The circuit includes a CMOS passgate or other transmission control and filtering means, one or more shunting transistors, and an output driver. The CMOS passgate, in conjunction with a first shunting transistor, allows an output enable command to control transmission of the data signal to the output driver. By properly tuning the CMOS passgate, bounce on the power supply and ground lines can be minimized. A second shunting transistor can be included to allow other data control signals, such as a write enable or chip select signal, to cease data output by the circuit. Additionally, a third shunting transistor, controlled by the data signal, can be included to allow fast turn off of the output driver.
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