Method for fabricating a semiconductor device having recessed gate electrode and elevated source and drain regions

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United States of America Patent

PATENT NO 7833868
APP PUB NO 20090023277A1
SERIAL NO

12165228

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Abstract

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A method for fabricating a semiconductor device, the method includes forming an isolation layer defining an active region over a substrate, forming a conductive layer over the substrate including the isolation layer, patterning the conductive layer to form a conductive pattern over the active region defined on both sides of a gate region, forming insulation spacers on a sidewall of the conductive pattern, forming a conductive layer for a gate electrode and a gate hard mask layer over the resulting structure including the conductive pattern, and patterning the gate hard mask layer and the conductive layer for the gate electrode to form a gate in the gate region of the substrate.

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Patent Owner(s)

  • HYNIX SEMICONDUCTOR INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kang, Kyung-Doo Ichon-shi, KR 5 6

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