Method and apparatus for analyzing delay in circuit, and computer product
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Apr 7, 2009
Grant Date -
Apr 12, 2007
app pub date -
Jan 30, 2006
filing date -
Oct 11, 2005
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An extracting unit extracts unprocessed capturing destination in a circuit. A tracing unit traces an output branch point from a capturing destination and a determining unit determines an estimated failure site and a non-failure site in the circuit. A detecting unit narrows down an estimated failure site using a fail address. It is determined whether an identifying unit has identified a failure site. If the failure site has not been identified, a delay failure simulation is performed and a comparing unit compares the comparison result of the tester measurement and the result in the delay failure simulation to determine consistency between the results. The identifying unit identifies the failure site based on the consistency.
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