Memory efficient streamlined transmitter with a multiple instance hybrid ARQ
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United States of America Patent
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Mar 4, 2008
Grant Date -
Sep 14, 2006
app pub date -
Mar 11, 2005
filing date -
Mar 11, 2005
priority date (Note) -
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Abstract
An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate an output signal in response to a first intermediate signal and a second intermediate signal. The second intermediate signal comprises a series of bit pairs. The second circuit comprises a first and a second encoder and may be configured to generate the second intermediate signal in response to a third intermediate signal. The third circuit may be configured to generate the first intermediate signal and the third intermediate signal in response to a first address signal and a second address signal. The third circuit comprises a first multiplexer and a second multiplexer.
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