Switched capacitor DRAM sense amplifier with immunity to mismatch and offsets
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United States of America Patent
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May 22, 2007
Grant Date -
Mar 2, 2006
app pub date -
Aug 31, 2004
filing date -
Aug 31, 2004
priority date (Note) -
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Abstract
A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor characteristics and offsets. The sense amplifier includes a cross-coupled pair of inverters with capacitors absorbing offset voltages developed as effects of the mismatches. When used in a dynamic random access memory (DRAM) device, this immunity to the mismatches and offsets allows the sense amplifier to reliably detect and refresh small signals.
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