Fabrication method for a semiconductor structure

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United States of America Patent

PATENT NO 7265023
APP PUB NO 20050245042A1
SERIAL NO

11099962

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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The present invention provides a fabrication method for a semiconductor structure having the steps of providing a semiconductor substrate (1); providing and patterning a silicon nitride layer (3) on the semiconductor substrate (1) as topmost layer of a trench etching mask; forming a trench (5) in a first etching step by means of the trench etching mask; conformally depositing a liner layer (10) made of silicon oxide above the resulting structure, which leaves a gap (SP) reaching into the depth in the trench (5); carrying out a V plasma etching step for forming a V profile of the line layer (10) in the trench (5); wherein the liner layer (10) is pulled back to below the top side of the silicon nitride layer (3); an etching gas mixture comprises C.sub.5F.sub.8, O.sub.2 and an inert gas is used in the V plasma etching step; the ratio (V) of C.sub.5F.sub.8/O.sub.2 lies between 2.5 and 3.5; and the selectivity of the V plasma etching step between silicon oxide and silicon nitride is at least 10.

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Patent Owner(s)

  • POLARIS INNOVATIONS LIMITED

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Haupt, Moritz Dresden, DE 9 261
Klipp, Andreas Dresden, DE 41 468
Sperlich, Hans-Peter Dresden, DE 14 95
Stavrev, Momtchill Dresden, DE 1 6
Wege, Stephan Weissig, DE 40 477

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