Digital data buffer with phase aligner
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United States of America Patent
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Sep 21, 2010
Grant Date -
Sep 4, 2008
app pub date -
Feb 8, 2008
filing date -
Feb 8, 2007
priority date (Note) -
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Abstract
A digital data buffer has at least one data path and a parallel reference data path. The data path includes a first and second data register, and the reference path includes a third data register. A learn cycle control signal is applied to a multiplexer for selecting between the data path and the reference data path and is also applied in parallel to control circuitry of a phase aligner. The learn cycle control signal is for adjusting the phase of a clock signal at a second clock output of a phase locked loop so as to optimize setup and/or hold timing at the data input of the second data register.
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