Arranging through silicon vias in IC layout

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United States of America Patent

PATENT NO 8136084
APP PUB NO 20110057319A1
SERIAL NO

12555981

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Abstract

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A portion of an IC layout that includes a plurality of through silicon vias (TSVs) is evaluated to identify linearly aligned TSVs. The portion of the IC layout is modified to reduce a number of the linearly aligned TSVs, resulting in less wafer breakage.

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Patent Owner(s)

  • GLOBALFOUNDRIES INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Dean,, Jr Donald R Essex Junction, US 1 5
Lindgren, Peter J Essex Junction, US 29 453
Miles, Glen L Hopewell Junction, US 17 276
Sprogis, Edmund J Essex Junction, US 94 2335
Stamper, Anthony K Essex Junction, US 613 6596

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