Reconfigurable datapath for processor debug functions
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United States of America Patent
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Nov 11, 2003
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N/A
app pub date -
Aug 24, 1999
filing date -
Sep 17, 1998
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Abstract
A reconfigurable datapath (13b), which may be alternatively configured for various debug modes. These modes include a breakpoint mode (20), counter mode (30a-30c), DMA mode (40), and PSA mode (50). Each configuration uses one or more of two bitcell units: a register bitcell unit (60) and a comparator bitcell unit (70). The inputs and interconnections of these bitcell units (60, 70) determine the configuration, and hence the mode, for which they are to be used.
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