Method for manufacturing dual-spacer structure
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United States of America Patent
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-
Dec 31, 2002
Grant Date -
Sep 26, 2002
app pub date -
Mar 23, 2001
filing date -
Mar 23, 2001
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A method of manufacturing a field effect transistor with a dual-spacer structure. A substrate having a first device region and a second device region is provided. The first device region comprises a first gate formed over the substrate and the second device region comprises a second gate formed over the substrate. A first dielectric layer is formed over the substrate. A second dielectric layer is formed on the first dielectric layer. A portion of the second dielectric layer is removed to expose a portion of the first dielectric layer in the second device region. A portion of the remaining second dielectric layer is removed to form a first spacer on the second dielectric layer on the sidewall of the first gate. A portion of the first dielectric layer is removed to form a second spacer on the sidewall of the second gate. The first spacer and the remaining second dielectric layer between the first spacer and the first gate together form a third spacer.
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