Simultaneous multiple thread processor increasing number of instructions issued for thread detected to be processing loop
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United States of America Patent
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Sep 6, 2011
Grant Date -
Feb 3, 2011
app pub date -
Oct 8, 2010
filing date -
Aug 24, 2007
priority date (Note) -
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Abstract
A processor simultaneously issues instructions to multiple threads in a same instruction execution cycle. An instruction issuer controls issuance of an instruction for each of the multiple threads. A detector detects, for each of the multiple threads, whether a loop processing is currently being executed. A unit causes the instruction issuer to increase a number of instructions to be issued when the detector detects that the loop processing is currently being executed.
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