Non-volative memory system configured to mitigate errors in read and write operations

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United States of America Patent

PATENT NO 11941281
APP PUB NO 20230315325A1
SERIAL NO

17711968

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Abstract

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A system and method for a memory system are provided. A memory device includes an array of non-volatile memory cells. A memory controller is connected to the array of non-volatile memory cells. The memory controller is configured to perform the steps of receiving a request to read a value of a memory flag, wherein the memory flag includes a 2-bit value stored in a first memory cell and a second memory cell of the array of non-volatile memory cells, reading a first value of the first memory cell, reading a second value of the second memory cell, and determining the value of the memory flag based on the first value and the second value. In embodiments, the memory flag may have more than 2-bits.

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Patent Owner(s)

  • NXP B.V.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ostertun, Soenke Wedel, DE 13 35

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