System on chip (SoC) device verification system using memory interface
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United States of America Patent
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Aug 7, 2012
Grant Date -
Jan 21, 2010
app pub date -
May 29, 2009
filing date -
Jul 16, 2008
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Abstract
A system on a chip (SoC) device verification system comprises: an SoC device model including one or more IPs and a memory controller; an external IP verification model receiving an instruction from the SoC device model and verifying operation of the one or more IPs included in the SoC device model; and a bus select model selecting one of the external IP verification model and an external device in response to a memory control signal received from the memory controller of the SoC device model.
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