Memory interface for a multi-threaded, self-scheduling reconfigurable computing fabric

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United States of America Patent

PATENT NO 11836524
APP PUB NO 20210064435A1
SERIAL NO

16997180

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Abstract

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Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative memory interface circuit comprises: a plurality of registers storing a plurality of tables, a state machine circuit, and a plurality of queues. The plurality of tables include a memory request table, a memory request identifier table, a memory response table, a memory data message table, and a memory response buffer. The state machine circuit is adapted to receive a load request, and in response, to obtain a first memory request identifier from the load request, to store the first memory request identifier in the memory request identifier table, to generate one or more memory load request data packets having the memory request identifier for transmission to the memory circuit, and to store load request information in the memory request table. The plurality of queues store one or more data packets for transmission.

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Patent Owner(s)

Patent OwnerAddress
MICRON TECHNOLOGY INC8000 SOUTH FEDERAL WAY BOISE ID 83707

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Brewer, Tony M Plano, US 161 2216

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