Controller limiting modification of cache based upon amount of dirty lines in the cache
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United States of America Patent
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Nov 14, 2000
Issued Date -
N/A
app pub date -
Dec 24, 1996
filing date -
Feb 20, 1991
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In allocating an area of a cache memory to each storage unit, proper allocation of the cache memory is made to each storage unit. If the amount of write-after data becomes equal to or more than a threshold value, an allocation limit is set to each disk unit. If CPU issues a data write request requiring the amount of data equal to or more than the allocation limit, the data write request is held in a wait state until the amount of write-after data becomes less than the allocation limit. Therefore, the allocation amount to the disk unit becomes neither too large nor too small. In this manner, proper allocation of the cache memory to each disk unit can be realized.
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