Robust latchup-immune CMOS structure
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United States of America Patent
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Feb 20, 2001
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app pub date -
Jan 11, 1999
filing date -
Jan 11, 1999
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Abstract
A method is disclosed to provide for more robust latchup-immune CMOS transistors by increasing the breakover voltage V.sub.BO, or trigger point, of the parasitic npn and pnp transistors present in CMOS structures. These goals have been achieved by adding a barrier layer to both the n-well and p-well of a twin-well CMOS structure, thus increasing the energy gap for electrons and holes of the parasitic npn and pnp transistor, respectively.
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