Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation
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United States of America Patent
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Mar 7, 2017
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Nov 5, 2015
app pub date -
Jun 26, 2015
filing date -
Sep 28, 2012
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Abstract
Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.
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