Semiconductor device and method of manufacturing the same
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Sep 18, 2007
Grant Date -
Aug 4, 2005
app pub date -
Mar 28, 2005
filing date -
Feb 27, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The present invention is to improve yield and reliability in a wiring step of a semiconductor device. When an Al wiring on an upper layer is connected through an connection pillar onto an Al wiring on a lower layer embedded in a groove formed on an interlayer insulation film, a growth suppression film having an opening whose width is wider than that of the Al wiring is formed on the interlayer insulation film and the Al wiring. In this condition, Al and the like are grown by a selective CVD method and the like. Accordingly, the connection pillar is formed on the Al wiring within the opening, in a self-matching manner with respect to the Al wiring.
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