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Abstract

The test system and method described herein reduces the production test time of semiconductor devices. More specifically, the apparatus method in accordance with the present invention reduces the data transfer time between the test body and the test mainframe. The test system includes a workstation, a handling device, a test body and a test mainframe. A communication channel links the workstation, the handling device, the test body and the test mainframe together for transferring control signals and data. The test mainframe sends control signals to the test body to send a m-bit packet of least significant bits for each n-bit code word, where m is proportional to the noise amplitude inherent in the system in terms of least significant bits. In the alternative, a user at the workstation can send control signals to the test body to send a m-bit packet for each n-bit code word. The test mainframe calculates the number of m-bit packets that can simultaneously be transferred over the communications channel to the test mainframe. Once the test mainframe captures this data, the test mainframe regenerates the original n-bit code word from this m-bit packetized data by determining an offset value to add to each m-bit packet to sum to the value of the original n-bit code word. The test mainframe further processes n-bit code words to determine whether the device passes a predetermined criteria of operability.

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First Claim