Method for checking an IC layout
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United States of America Patent
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Jun 3, 2008
Grant Date -
Mar 10, 2005
app pub date -
Aug 24, 2004
filing date -
Sep 8, 2003
priority date (Note) -
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status (Latency Note)
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Abstract
A method of the invention is used for checking a wire layout causing high wire resistance. The method includes the steps of: selecting a first metal layer, a second metal layer and a third metal layer, wherein each of the first and third metal layer includes a power wire for transmitting power, and the second metal layer is adjacent to the first and third metal layers; selecting one region in the second metal layer, wherein the first and the third metal layers have the power wires at positions corresponding to the region and the second metal layer has no wire at the region; and disposing a conductive metal layer coupled to the first and third metal layer in the region for lowering the equivalent wire resistance.
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