High density architecture design for 3D logic and 3D memory circuits

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United States of America Patent

PATENT NO 11764200
SERIAL NO

17652864

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Abstract

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Techniques herein include methods of forming higher density circuits by combining multiple substrates via stacking and bonding of individual substrates. High voltage and low voltage devices along with 3D NAND devises are fabricated on a first wafer, and high voltage and low voltage devices and/or memory are then fabricated on a second wafer and/or third wafer.

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Patent Owner(s)

  • TOKYO ELECTRON LIMITED

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fulford, H Jim Marianna, US 234 1647
Gardner, Mark Cedar Creek, US 18 382

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