Clocked and non-clocked repeater insertion in a circuit design

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United States of America Patent

PATENT NO 6910196
APP PUB NO 20040225981A1
SERIAL NO

10431913

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A method and apparatus to obtain minimum cycle latency and maximum required time at a driver for an assignment of clocked and non-clocked repeaters in a topology comprising, determining whether a node in the topology is a leaf, and assigning covers if the node is a leaf. Determining whether the node in the topology comprises one branch or two branches. Assigning covers to each node and eliminating inferior covers. Merging covers, and deleting inferior covers taking into account a difference in interconnect latency associated with the covers. The above method may be modified with a heuristic to insert repeaters in a topology for a given latency at each driver-receiver pair.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cocchini, Pasquale Hillsboro, OR 3 18

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