Methods for forming interconnection structures in an integrated cluster system for semicondcutor applications
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United States of America Patent
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Nov 29, 2016
Grant Date -
Sep 17, 2015
app pub date -
May 13, 2014
filing date -
Mar 11, 2014
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Abstract
Embodiments of the present invention provide methods for forming an interconnection structure in semiconductor devices without breaking vacuum with minimum oxidation/atmosphere exposure. In one embodiment, a method for forming an interconnection structure for semiconductor devices includes supplying a barrier layer etching gas mixture into a first processing chamber having a substrate disposed therein to etch portions of a barrier layer exposed by a patterned metal layer until the underlying substrate is exposed, the first processing chamber disposed in a processing system, and forming a liner layer on the substrate covering the etched barrier layer in a second processing chamber disposed in the processing system.
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