Region based shrinking methodology for integrated circuit layout migration
Number of patents in Portfolio can not be more than 2000
United States of America
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Mar 15, 2022
Grant Date -
Sep 10, 2020
app pub date -
May 21, 2020
filing date -
May 21, 2020
priority date (Note) -
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Abstract
A method of making a semiconductor device includes receiving a first layout of a device in a first technology node, wherein the first layout comprises a plurality of first conductive patterns spaced along a first direction and a plurality of first interconnect patterns connecting at least two of the plurality of first conductive patterns. The method includes identifying a plurality of second conductive patterns from the plurality of first conductive patterns according to a second technology node different from the first technology node. The method includes determining a scaling factor for the first layout in the first direction based on the plurality of first conductive patterns and the plurality of second conductive patterns. The method includes adjusting the plurality of first interconnect patterns along the first direction using the scaling factor to determine a plurality of second interconnect patterns connecting at least two of the plurality of second conductive patterns.
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