Semiconductor memory device for reducing effect of leakage current
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United States of America Patent
Stats
-
Jan 2, 2024
Grant Date -
Dec 22, 2022
app pub date -
Dec 9, 2021
filing date -
Jun 21, 2021
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A semiconductor memory device includes memory cell arrays including a first memory cell and a first word line connected to the first memory cell, a first wiring electrically connected to the first word lines corresponding to the memory cell arrays, a driver circuit electrically connected to the first wiring, second wirings electrically connected to the first wiring via the driver circuit, a voltage generation circuit including output terminals disposed corresponding to the second wirings, and first circuits disposed corresponding to the memory cell arrays. The voltage generation circuit is electrically connected to the first word lines via a first current path including the second wirings, the driver circuit, and the first wiring. The voltage generation circuit is electrically connected to the first word lines via a second current path including the second wirings and the first circuits and without including the driver circuit.
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