Contact structure of a wiring and a thin film transistor array panel including the same

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7507996
APP PUB NO 20040140575A1
SERIAL NO

10754572

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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First, a conductive material made of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed, and a semiconductor layer and an ohmic contact layer are sequentially formed. Next, a conductor layer including a lower layer of Cr and an upper layer of aluminum-based material is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad, respectively. Next, an amorphous silicon layer is deposited, an annealing process is executed to form inter-layer reaction layers on the drain electrode, the gate pa and the data pad, which are exposed through the contact holes. Then, the amorphous silicon layer is removed. Next, IZO is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively and electrically connected to the drain electrode, the gate pad and the data pad via the inter-layer reaction layers.

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Patent Owner(s)

  • SAMSUNG DISPLAY CO., LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hong, Mun-Pyo Kyungki-do , KR 125 2160
Kim, Sang-Gab Kyungki-do, KR 114 744

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