Use of an insulating spacer to prevent threshold voltage roll-off in narrow devices

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United States of America Patent

PATENT NO 6251747
SERIAL NO

09432666

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Abstract

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A method of forming a semiconductor device minimizes oxide recessing in a trench of a semiconductor device. In one embodiment, forming a nitride spacer surrounding the top trench corner oxide in a shallow trench isolation region protects the corner oxide from being etched during processing. Oxide recessing in the trench is undesirable since it results in high electric fields around the sharp top corners of the trenches and V.sub.t roll-off of the transistors. According to one example embodiment, STI regions filled with an HDP oxide and having undergone planarization, are masked. The masking substantially covers the HDP oxide and overlaps at least portions of nitride regions. Unmasked areas of the nitride regions are etched away forming nitride spacers on both sides of the HDP oxide fill.

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Patent Owner(s)

  • NXP B.V.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Nouri, Faran Los Altos, CA 18 414
Zheng, Tammy Fremont, CA 12 116

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