Semiconductor arrangement and method for making
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United States of America Patent
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Oct 25, 2022
Grant Date -
Jun 4, 2020
app pub date -
Nov 13, 2019
filing date -
Nov 30, 2018
priority date (Note) -
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status (Latency Note)
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Abstract
A method for fabricating a semiconductor arrangement includes removing a portion of a first dielectric layer to form a first recess defined by sidewalls of the first dielectric layer, forming a first conductive layer in the first recess, removing a portion of the first conductive layer to form a second recess defined by the sidewalls of the first dielectric layer, forming a second conductive layer in the second recess, where the second conductive layer contacts the first conductive layer, forming a second dielectric layer over the second conductive layer, removing a portion of the second dielectric layer to form a third recess defined by sidewalls of the second dielectric layer, where the second conductive layer is exposed through the third recess, and forming a third conductive layer in the third recess, where the third conductive layer contacts the second conductive layer.
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