Single-drive level shifter with low dynamic impedance
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United States of America Patent
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-
Nov 3, 1992
Grant Date -
N/A
app pub date -
Jul 24, 1991
filing date -
Jul 27, 1990
priority date (Note) -
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status (Latency Note)
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Abstract
A level shifter, particularly suited for driving power stages for supplying power to integrated circuits, includes a DMOS transistor (40) which is driven by a digital signal source (42) and has a load resistor (44) as its drain load. A shifted output signal develops at the ends of said load resistor. The drain (V1) of the DMOS transistor is connected to the input of an inverter (46), while a Zener diode (54) and a second transistor (52) are connected in parallel with the load resistor (44), the gate of the second transistor (52) being driven by the output of the inverter (46). The output of the inverter (46) can be connected to the input of a drive stage (48), the output of which drives a power stage (50) for supplying power to an integrated circuit.
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